 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4514B MSI 1-of-16 decoder/demultiplexer with input latches Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 1-of-16 decoder/demultiplexer with input latches DESCRIPTION The HEF4514B is a 1-of-16 decoder/demultiplexer, having four binary weighted address inputs (A0 to A3), a latch enable input (EL), and an active LOW enable input (E). The 16 outputs (O0 to O15) are mutually exclusive active HIGH. When EL is HIGH, the selected output is determined by the data on An. When EL goes LOW, the HEF4514B MSI last data present at An are stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is HIGH. At E HIGH, all outputs are LOW. The enable input (E) does not affect the state of the latch. When the HEF4514B is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs. Fig.1 Functional diagram. HEF4514BP(N): HEF4514BD(F): HEF4514BT(D): 24-lead DIL; plastic (SOT101-1) 24-lead DIL; ceramic (cerdip) (SOT94) 24-lead SO; plastic (SOT137-1) ( ): Package Designator North America Fig.2 Pinning diagram. APPLICATION INFORMATION Some examples of applications for the HEF4514B are: PINNING A0 to A3 E EL O0 to O15 address inputs enable input (active LOW) latch enable input outputs (active HIGH) FAMILY DATA, IDD LIMITS category MSI See Family Specifications * Digital multiplexing. * Address decoding. * Hexadecimal/BCD decoding. January 1995 2 Philips Semiconductors Product specification 1-of-16 decoder/demultiplexer with input latches HEF4514B MSI Fig.3 Logic diagram. Fig.4 Logic diagram (one latch). January 1995 3 Philips Semiconductors Product specification 1-of-16 decoder/demultiplexer with input latches TRUTH TABLE INPUTS E H L L L L L L L L L L L L L L L L Notes 1. EL = HIGH; H = HIGH state (the more positive voltage); L = LOW state (the less positive voltage); X = state is immaterial AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays An, EL On HIGH to LOW 5 10 15 5 LOW to HIGH E On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tPLH tPHL tPLH tPHL 260 95 65 270 95 65 175 65 45 200 70 50 520 190 130 550 190 130 350 130 90 400 140 100 ns ns ns ns ns ns ns ns ns ns ns ns 233 ns 84 ns 57 ns 243 ns 84 ns 57 ns 148 ns 54 ns 37 ns 173 ns 59 ns 42 ns + + + + + + + + + + + + SYMBOL TYP. MAX. A0 X L H L H L H L H L H L H L H L H A1 X L L H H L L H H L L H H L L H H A2 X L L L L H H H H L L L L H H H H A3 X L L L L L L L L H H H H H H H H O0 L H L L L L L L L L L L L L L L L O1 L L H L L L L L L L L L L L L L L O2 L L L H L L L L L L L L L L L L L O3 L L L L H L L L L L L L L L L L L O4 L L L L L H L L L L L L L L L L L O5 L L L L L L H L L L L L L L L L L O6 L L L L L L L H L L L L L L L L L OUTPUTS O7 L L L L L L L L H L L L L L L L L O8 L L L L L L L L L H L L L L L L L O9 L L L L L L L L L L H L L L L L L HEF4514B MSI O10 O11 O12 O13 L L L L L L L L L L L H L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L H L L O14 L L L L L L L L L L L L L L L H L O15 L L L L L L L L L L L L L L L L H TYPICAL EXTRAPOLATION FORMULA (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL January 1995 4 Philips Semiconductors Product specification 1-of-16 decoder/demultiplexer with input latches AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Output transition times HIGH to LOW LOW to HIGH Set-up time An EL Hold time An EL Minimum EL pulse width; HIGH 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 tWELH thold tsu 120 40 30 0 0 0 120 40 30 tTLH tTHL SYMBOL MIN. TYP. MAX. 90 35 25 85 35 25 60 20 15 60 20 15 60 20 15 180 65 50 170 70 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns HEF4514B MSI TYPICAL EXTRAPOLATION FORMULA 40 ns + (1,0 ns/pF) CL 14 ns + (0,42 ns/pF) CL 11 ns + (0,28 ns/pF) CL 35 ns + (1,0 ns/pF) CL 14 ns + (0,42 ns/pF) CL 11 ns + (0,28 ns/pF) CL see also waveforms Fig.5 VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 1100 fi + (foCL) x VDD2 5500 fi + (foCL) x VDD2 16 000 fi + (foCL) x VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 5 Philips Semiconductors Product specification 1-of-16 decoder/demultiplexer with input latches HEF4514B MSI Fig.5 Waveforms showing minimum pulse width for EL, set-up and hold times for An to EL. Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 6 |
Price & Availability of HEF4514B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |